
Universal Chiplet Interconnect Express, kapa UCIe, ke mokhoa o amanang o bulehileng oa indasteri oa ho hekella chiplets ka hare ho paketeng e le 'ngoe ea semiconductor. Chiplet ke die e nyane e sebetsang e ka fanang ka ts'ebetso, memoria, litšoantšo, marang-rang, ts'ireletso, I/O, kapa ts'ebetso ea mekhoa.
UCIe e fa litaelo tse fapaneng tsa die interface e amanang hore li ka buisana joalo ka likarolo tsa tsamaiso e le nngwe. E ka tsamaisa PCI Express, Compute Express Link, le mekhoa ea ho tšoara liphetho pakeng tsa chiplets, ho kenyeletsoa le die tse hlahiloeng ke bahlahisi ba fapaneng kapa ka theknoloji e fapaneng.

Setšoantšo sa 2. Mehato ea Moralo oa Chiplet
Chips tse kholo tse monolithic li ntse li thata le ho feta ho li etsa ha boholo ba die le palo ea transistor e eketseha. Die e kholo e sebelisa sebaka se eketsehileng sa wafer mme e na le monyetla o moholo oa ho ba le khethollo, e ka fokotsang yield le ho eketsa theko ea sesebelisoa se seng le se seng se ka sebelisoang.
Chiplets li arola moralo o moholo ho die tse smaller. Likhoele tse sebetsa li ka sebelisa node e tsoetseng pele, ha analog, I/O, ts'ireletso, taolo, le umsebenzi o mong li ka sebelisa li-node tse mature le tse theko e tlase. Chiplets tse bontšitsoeng li ka boela li sebelisoa hape ho lihlahisoa tse 'maloa, ho fokotsa tlhoko ea ho hlahisa processor e feletseng nako le nako.
Tlhoko e setseng ke puisano. Li-link tsa proprietary die-to-die li ka fetola ho boreleli pakeng tsa chiplets ho tloha lihlopha kapa bahlahisi ba fapaneng. UCIe e fa interface e amanang bakeng sa ho hokela CPU, GPU, memoria, I/O, marang-rang, le die tsa ts'ireletso ka hare ho paketeng e le 'ngoe.

Setšoantšo sa 3. UCIe Link Initialization, Training, Data Transfer, le Error Recovery
UCIe e theha khoele e potlakileng pakeng tsa chiplets tse peli. Ha sistimi e fola, khoele e qala, 'me lehlakoreng le leng le le leng le tlaleha litekanyo tsa data tse tšehetsang, mekhoa ea lane, mekhoa, le mefeatures e sebetsang. Khoele e khetha lintlha tse tšehetsang ke bobeli ba chiplets.
Litlhaku li koetlisoa hore moaméli a felisise liphetho tse khethiloeng le ho fumana data e phatlalalitsoeng. Hang ha koetliso e fela, PCIe, CXL, kapa liphetho tse phallang li ka tsamaea ho tloha pakeng tsa kopano.
Nakong ea ts'ebetso, kwebo e hlahloba boits'episo ba data, e laola liphoso, 'me e ka fokotsa matla ha liphetho li se li ntse li le khutso.
UCIe e na le li-releases tse 'ne tsa specs: UCIe 1.0, 1.1, 2.0, le 3.0. Setšoantšo se seng se kenya bokhoni bo bocha ha se ntse se boloka ts'ebetsong le li-releases tse tlang pele.
| Mofuta |
Phethahatso |
Bokhoni bo phahameng ba Data Rate |
Liphetoho tse amanang |
Ts'ehetso ea Packaging |
| UCIe 1.0 |
2022 |
Ho fihlela 32 GT/s, ho itšetlehile ka mokotla |
E hlahisitse PHY, adapter, PCIe, CXL, mekhahlelo ea phallang, mohlala oa software, le mekgwa e amanang |
Li-packages tsa 2D kapa 2.5D tse tloaelehileng le tse tsoetseng pele |
| UCIe 1.1 |
Phato 2023 |
Ho fihlela 32 GT/s |
Hlahisitse phallang e molemo, ho hapa, ts'ehetso ea mekhahlelo e mengata, ho bona bophelo, ho lokisa link, le tlhahlobo ea compliance |
Likhetho tse hlahisitsoeng bakeng sa packages tse theko e tlase |
| UCIe 2.0 |
Phato 2024 |
Ho fihlela 32 GT/s |
Kenyelletso ea UCIe DFx Architecture bakeng sa tlhahlobo, telemetry, manejement, le debugging |
Kenyelletso ea UCIe-3D bakeng sa ketso e ntle le mekhahlelo ea hybrid-bond |
| UCIe 3.0 |
Phato 5, 2025 |
48 le 64 GT/s |
Kenyelletso ea ho hlophisa bohloko, ho ntlafatsa taolo e fokolang ea matla, sebaka se telele sa sideband, downloading e boholo ba firmware, ho thibela ka potlako, le matšoenyeho a matšoenyeho |
Ts'ehetso e phahameng ea UCIe-S le UCIe-A |
Chiplets tse ipapisitseng le mefuta e fapaneng ea UCIe li ka buisana, empa khelo e sebetsa feela ho li-rate tsa data le likarolo tse tšehetsang ke lisebelisoa tse peli. Moenjiniere ba lokela ho netefatsa hore PHY, node ea ts'ebetso, theknoloji ea packaging, le lisebelisoa tsa netefatso li tšehetsa mofuta oa UCIe o hlokahalang.

Setšoantšo sa 4. UCIe Protocol, Adapter, FDI, RDI, le PHY Architecture
UCIe e arohanya ts'ebetso ea protocol, mananeo a khetho, le liphetho tsa motlakase ka mehaho e meraro e meholo: lebotho la protocol, lebotho la die-to-die adapter, le lebotho la 'mele.
Labetso la Protocol
Labetso la protocol le tsamaisa liphetho tse fanoang lipakeng tsa chiplets. Sena se ka kenyelletsa Transactions tsa PCIe, CXL mehloli ea mehlolo le liphetho tsa phallo, kapa data e tsoang ho protocol e 'nang e tšehetsa.
UCIe ha e fane ka PCIe kapa CXL. E fa khokahano ea mokotla e sebelisetsoang ho jara liphetho tsa bona lipakeng tsa dies.
Labetso la Die-to-Die Adapter
Die-to-die adapter e eme lipakeng tsa lebotho la protocol le lebotho la 'mele. E lokisetsa data ea protocol bakeng sa phallo le ho laola khelo.
Mesebetsi ea eona e ka kenyelletsa ho buisana ka protocol, ho lokisa data, taolo ea phallo, tlhahiso le ho lekola CRC, ho tsamaisa ho khutlisoa, ho tlaleha liphoso, taolo ea state-link, le tsamaiso ea state-matla. Mesebetsi e nepahetseng e itšetlehile ka mokhoa oa protocol o khethiloeng le mofuta oa UCIe.
Labetso la 'Mele
Labetso la 'mele le romela le ho amohela liphetho tse motlakase tse kenang ho pakete. E kenyelletsa bahlahisi, baameli, likhoele tsa nako, logic ea lane, mesebetsi ea calibration, le khokahano ea packaging.
Channel ea mainband e jara data e potlakileng. Channel ea sideband e jara taolo, ho qala, ho koetlisa, manejement, le πληροφορία ea maemo.
Litsela le Lisebelisoa
Khelo ea UCIe e tšoenya litsela tse ngata tse kopanyang ho modules. Ho eketsa palo ea litsela tse sebetsang ho phahamisa bandwidth eohle empa hape ho hlokahala sebaka sa die-edge se eketsehileng, bumps, routing, clocking, le matla a PHY.
FDI le RDI
Interface ea Flit-Aware Die-to-Die, kapa FDI, e kopanya bloko ea protocol le adapter. Interface ea Raw Die-to-Die, kapa RDI, e kopanya adapter le PHY.
Li-interface tse bashaneng li lumella bloko ea protocol, controller, le PHY ho hlahisoa ka mokhoa o fapaneng ha li ntse li boloka khokahano e itseng lipakeng tsa tsona.

Setšoantšo sa 5. UCIe-S vs UCIe-A vs UCIe-3D Ts'ebetso ea Packaging
UCIe e tšehetsa mekhahlelo ea packaging e meraro: UCIe-S bakeng sa li-packages tse tloaelehileng, UCIe-A bakeng sa li-packages tse tsoetseng pele, le UCIe-3D bakeng sa dies tse fanyehileng ka potoloho. Khetho e nepahetseng e itšetlehile ka bandwidth e hlokahalang, sebaka sa die-edge se fumanehang, ts'ebetso ea tlhahiso, meeli ea futhumatsang, le tšebeliso ea packaging.
| Melemo ea Qeto |
UCIe-S |
UCIe-A |
UCIe-3D |
| Mofuta oa package |
Package e tloaelehileng |
Package e tsoetseng pele |
Package e bataletseng ea borai |
| Tlhophiso ea die |
Dies li behiloe ka lehlakoreng la organic substrate |
Dies li behiloe ka lehlakoreng ka sebelisa interposer, borai, kapa fine redistribution layer |
Masela a behiloeng ka bokahohle |
| Bakeng sa lekanngoa le lelelele |
Ho fihlela ho amohelehang 25 mm |
Ho fihlela ho amohelehang 2 mm |
E itšetlehile ka sebopeho sa die stack le mokhoa oa ho kopanya |
| Bokhoni ba sehokelo |
Tlaase |
Phahameng |
Bokhoni bo phahameng ka ho fetisisa |
| Morero oa matla a sehokelo |
Hoo e ka bang 0.5 ho isa ho 1 pJ/bit |
Hoo e ka bang 0.25 ho isa ho 0.5 pJ/bit |
Mohlomong e tlase kaha ho na le likhokahano tse amanang le bokahohle |
| Theko e amanang le sephutheloana |
Tlaase |
Phahameng |
Hangata e phahameng ka ho fetisisa |
| Bothata ba ho routing |
Bohareng |
Phahame |
Haholo-holo |
| Bothata ba mocheso |
Bohareng |
Phahameng |
E phahameng ka ho fetisisa kaha masela a behiloeng a etsa hore ho ntlafatsa mocheso ho be thata |
| Bothata ba teko le pokello |
Tlaase |
Phahameng |
E phahameng ka ho fetisisa |
| E loketseng haholo |
Liphetho tse amanang le bandwidth le theko haholo ka mokhoa oa chiplet |
Masela a khutsufatsa, a pharaletse, le a phahameng-tlhahiso ka sehokela die-to-die |
Lintlha tse hlakileng le lintlha tse amanang le sebaka se lekanyelitsoeng sa die-edge |
UCIe-S
UCIe-S e lumellana le tlhahiso e tloaelehileng ea substrate e organic le mekhoa e thehiloeng ho pokello. Mofuta oa PHY, mekhoa e khutliloeng, phello ea matla, ho phahama ha bump, le lisebelisoa tsa substrate li hloka ho laoloa ka hloko bakeng sa ho boloka boleng ba sehokelo.
UCIe-A
UCIe-A e hloka ho rera haufi haufi empa har’a chiplet, PHY, sephutheloana, le marang-rang a matla. Makarolo a bump, ho routing ho semang, litsela tsa nkoa, ho hapa hole, le meeli ea pokello li lokela ho hlahlojoa kapele ka ho sebelisa sephutheloana se reriloeng.
UCIe-3D
UCIe-3D e hloka ho beha ka hloko mesebetsi e phahameng ea matla, litlhaku tsa mocheso, litsela tsa matla, le marang-rang a nako ho pota masela a behiloeng. Teko e lokela ho reranoa le pele ho pokello ka ho sebelisana le die tse tsejoang hantle, ho iketsetsa teko, ho arola mefokolo, le likarolo tse lokisang.
Mofuta oa leleng le litlhaku tsa matla a lisebelisoa tsa tafole ke liphetho tse amanang. Liphetho tsa nnete li itšetlehile ka PHY, lebelo la lane, node ea sehlahisoa, pitch ea bump, lisebelisoa tsa sephutheloana, routing, voltage, le mocheso.
Ts'ebetso ea UCIe e itšetlehile ka lebelo la lane, palo e felletseng ea mekhahlelo e amanang, moralo oa PHY, sephutheloana sa channel, le protocol e tsamaisitsoeng. UCIe 3.0 e ts'ehetse mekhoahlalo ea data e lebelo la 48 le 64 GT/s bakeng sa UCIe-S le UCIe-A. Melemo ena ke likhono tsa ho tsamaisa le lane e 'ngoe le e 'ngoe, eseng bandwidth ea qetelo e fumanehang ho data ea kopo.
Bandwidth ea theori ka lebelo le le leng e ka baloang joaloka:
Bandwidth ea theori ka lebelo = Lebelo la lane × Palo e felletseng ea mekhahlelo e amanang ÷ 8
Palo e felletseng ea mekhahlelo e amanang e kenyelletsa mekhahlelo e mengata e amanang le mofuta o mong le o mong o sebelisitsoeng ke sehokelo:
Palo e amanang ea mekhahlelo = Leme la ts'ebetso ka module × Palo ea mekhahlelo e amanang
Joalo ka mohlala, mekhahlelo e 'meli e amanang le lekhala la 16 moelelo e fa:
Palo e amanang ea mekhahlelo = 16 × 2 = 32 likhukhuni
Formula ea bandwidth e nahana ka bit e rometsoeng ka potlako. E sitwa ho nka lisebelisoa tsa protocol, framing, CRC, retries, flow control, kapa mekhahlelo e sa sebetseng. Ho arola ka bosupa ho fetolela gigabits ka segokanyipanelo ho gigabytes ka segokanyipanelo.
Bakeng sa module e le 'ngoe e amanang ea 16-lane:
• Ho 64 GT/s: 64 × 16 ÷ 8 = 128 GB/s bandwidth e theorized ka lebelo le le leng
• Ho 48 GT/s: 48 × 16 ÷ 8 = 96 GB/s bandwidth e theorized ka lebelo le le leng
Bandwidth ea nnete e amanang e tlase hobane karolo e 'ngoe ea sehokelo e sebelisetsoa ho sebetsana le protocol, framing, CRC, retries, flow control, le mekhahlelo e sa sebetseng.
Bandwidth ea payload = Bandwidth ea theori × Bokhoni ba payload
Sephetho se amanang le bandwidth ea payload se lokela ho bolela mofuta oa UCIe, protocol, palo e felletseng ea mekhahlelo, palo ea mekhahlelo, lebelo la sepheo, boholo ba packet, sekhahla sa retry, nako e sa sebetseng, le maemo a teko.
Nahana hore chiplet e hloka 80 GB/s ea bandwidth ea payload le bokhoni bo lebelletsoeng ba payload ke 80%.
Bokhoni ba 80% ba payload bo sebelisitsoeng mohlala ona ke mehato e amanang le moralo, eseng boleng ba UCIe bo tiileng. Bokhoni ba nnete bo itšetlehile ka protocol, boholo ba packet, framing, CRC, retries, flow control, mekhahlelo e sa sebetseng, le mokhathala oa lipalo.
Bandwidth e amanang le theori e hlokahalang = 80 GB/s ÷ 0.80 = 100 GB/s
| Sehokelo sa Configuration |
Bandwidth ea Theoretical Raw ka Lebelo |
Payload ka 80% Bokhoni |
Sephetho |
| 16 mekhahlelo e amanang ka 48 GT/s |
96 GB/s |
76.8 GB/s |
Ha e lekanele |
| 16 mekhahlelo e amanang ka 64 GT/s |
128 GB/s |
102.4 GB/s |
E fihlela morero |
Khokahano e nang le 16 liporo tse sebetsang ka 64 GT/s e habisa ka botlalo 80 GB/s eo e e hlokang le ho fa sebaka sa ho khanna. Le fa, PHY, mohokahanyi, node ea ts'ebetso, le pakete tsohle li tlameha ho tšehetsa se hlokahalang. Mohala oa sephutheloana o lokela hape ho boloka boleng bo lekaneng ba mahlale ka 64 GT/s.
| Ts'ebetso Fektheri |
Phello e Khethiloeng |
| Phokotso ea lichi |
Liphetho tse phahameng li eketsa bandwidth empa li hloka boleng bo botle ba mahlale |
| Liphokotso tse totale |
Liphokotso tse ngata li eketsa bandwidth, matla a PHY, ho tsamaisa, ho sebelisa bump, le sebaka sa die-edge |
| Palo ea mekhahlelo |
Mekhahlelo e mengata e eketsa palo ea lipokotso le bandwidth e fumanehang |
| Efficacité ea payload |
Ela letho hore na ke bokae ba raw bandwidth bo fumanehang bakeng sa data ea kopo |
| Latency |
E ipapisitse le protocol, adapter, PHY, buffers, likoloko, le ho fumana hape |
| Bokhoni ba bandwidth |
E bontša hore na ke bokae ba bandwidth bo ka fang die edge |
| Matla ka each bit |
E ama ho sebeletsoa ha khokahano le mocheso oa sephutheloana |
| Mohala oa sephutheloana |
E ama lahleho, liphetoho, crosstalk, le margin ea signal |
Latency ea UCIe e kenyelletsa ho lieha ho feta karolo ea protocol, die-to-die adapter, PHY, buffers, likoloko, le mohala oa sephutheloana. Ho fumana hape ho eketsa ho lieha ha data e senyehileng e tlameha ho fetisoa hape.
Kamohelo e khuts'oane ea sephutheloana e fokotsa ho lieha le lahleho ea signal. Le fa, buffering, ho ikamahanya ha likoloko, ts'ebetso ea protocol, le litsela tse joalo ka lemati li ka eketsa latency e lekaneng. Liphetho tsa teko li lokela ho laela hape hore na latency e qala le ho fela kae hobane latency ea PHY-to-PHY e fapane le latency ea sephalapheli.
UCIe, PCIe, le CXL li sebeletsa mehopolo e fapaneng. UCIe e kopanya chiplets ka hare ho sephutheloana se le seng, PCIe e kopanya prosesa le lisebelisoa tsa I/O, le CXL e tšehetsa puisano e tšoanang lipakeng tsa prosesa, tse amanang, le mmele. UCIe e ka tsamaisa sepheo sa PCIe le CXL lipakeng tsa die.
| Ponahalo Phetha |
UCIe |
PCIe |
CXL |
| Morero o Moholo |
Kamohelo ea die-to-die chiplet |
Khamphani ho ea ho sesebelisoa sa I/O |
Kamohelo e amanang, e amanang le mmala |
| Sebaka se tloaelehileng |
Ka hare ho pakete e le 'ngoe ea semiconductor |
Borai, likarete, likhokelo, le mekato |
Likhokelo tsa lisebelisoa tse kantle kapa likhokelo tsa chiplet ka UCIe |
| Khamphani e amanang |
Mekhatlo ea sephutheloana, borai, interposers, kapa mesebetsi e emelang tšepe |
Liphokotso tse phahameng tsa borai |
E sebelisa signaling ea PCIe ka kantle le e ka sebelisa UCIe ka hare |
| Phahamiso |
Ha e fa phahamiso ka eona ka bo eona |
PCIe e tloaelehileng ha e na cache e amanang |
E tšehetsa cache le mmele e amanang |
| Mekhoa e Tloaelehileng |
CPU, GPU, mmele, I/O, le li-chiplet tse amanang |
SSDs, GPUs, le li-adapter tse amanang |
Tokelo ea mmele, pooling, le li-accelerators |
Sebelisa PCIe bakeng sa lisebelisoa tse tloaelehileng tsa I/O, CXL ha ho hlokahala ho fumana litšoantšo kapa cache, le UCIe ha mesebetsi ena e arotsoe lipakeng tsa chiplets ka hare ho sephutheloana se le seng.
UCIe le Bunch of Wires, kapa BoW, ke mekhahlelo e amanang le die-to-die. UCIe e fa mohla e kenyelletsang e phahameng ka ts'ebetso e hlalosang protocol, taolo ea khokahano, mesebetsi ea software, le teko e amanang. BoW e shebane haholo haholo le interface ea motlakase ea die-to-die le e fa bahlahisi boiketlo bo eketsehileng maemong a holimo a protocol.
| Ponahalo Phetha |
UCIe |
BoW |
| Scope |
PHY, adapter, protocols, taolo, le compliance |
Haholo-holo die-to-die motlakase le maemong a khokahaneng |
| Tšepo ea protocol |
PCIe, CXL, le streaming |
Protocols tse tloaelehileng kapa tse ikhethileng |
| Matla a Maholo |
Multi-vendor interoperability |
Tlhophiso e ka fetohang le e ikhethileng |
| E loketse haholo bakeng sa |
Platforme ea chiplet e atolosoang |
Chiplet e ikhethileng le disaggregated SoC design |
UCIe hangata ke khetho e molemo ha protocol e amanang le ho kopana le matla a multi-vendor a hlokeha. BoW e ka loketse mehlala e hlokang taolo e eketsehileng ka khokahano le faele e saheloang holimo.

Setšoantšo sa 6. Likopo tse Tloaelehileng tsa UCIe
UCIe e sebelisoa mechanteng e arotang ts'ebetso, mmele, marang-rang, le mesebetsi ea I/O lipakeng tsa die tse 'maloa.
| Sehlopha sa kopo |
Hlokomela ea morero o moholo |
Kamoo UCIe e thusang |
| AI, GPUs, le HPC |
Ts'ebetso e phahameng ea data lipakeng tsa computation, cache, mmele, le I/O |
E kopanya computation le chiplets tse amanang le mmele ka likhokelo tse khuts'oane, tse telele |
| CPUs le prosesa ea data-center |
Meralo ea modular processor e nang le mekhahlelo e ikhethileng ea computation, taolo, le I/O |
E hokahanya processor, cache, memory-controller, ts'ireletso, le I/O chiplets |
| Me系统 ea mehopolo |
Bophahamo bo bong kapa bokhoni ho feta tseo die e le 'ngoe e ka fanang ka tsona |
E hokahanya compute dies le cache, memory-controller, kapa memory-expansion chiplets |
| Networking le telecom |
Arohana mehato ea dijithale ho tswa SerDes, timing, le mekhahlelo ea interface |
E hokahanya packet-processing, networking, ts'ireletso, le high-speed I/O dies |
| Automotive le edge computing |
Kopanya mekhahlelo e khethehileng ho latela matla le meeli ea paket |
E hokahanya compute, graphics, sensor-processing, networking, mehopolo, le I/O dies |
| Optical I/O |
Fokotsa lahleheloa le matla a mehala e mekhutšoanyane |
E hokahanya processor kapa switch die le optical I/O chiplet e ikhethileng |
UCIe implementation e kenyelletsa moetsi, PHY, le lisebelisoa tsa netefatso tse hlokahalang bakeng sa chiplet link. Tsena li tlameha ho tšehetsa Version ea UCIe e le 'ngoe, protocol, paket, process node, sepheo sa ts'ebetso, le maemo a ho sebetsa.
Mohato 1: Netefatsa UCIe Version
Sheba hore bobeli chiplets li tšehetsa UCIe version e hlokahalang. Haeba mefuta e fapaneng e sebelisoa, sehokelo se ka sebelisa feela litekanyetso le likarolo tse tšehetsang ka bobeli.
Mohato 2: Bala Bophahamo bo Hlokahalang
Netefatsa hore lane rate, palo ea mehato, le palo ea mekhahlelo li ka fana ka payload bandwidth e hlokahalang. Tlohela margine e lekanyelitsoeng bakeng sa protocol overhead, retries, le liphetoho tsa seketso.
Mohato 3: L matched the package type
Etsa sicher PSD e tšehetsa paket e khethiloeng, leha e le UCIe-S, UCIe-A, kapa UCIe-3D. Paket e lokela ho kopana le litlhoko tse hlokahalang tsa routing, bolelele ba kanale, bump pitch, le meeli ea boleng ba senotlolo.
Mohato 4: Sheba Ts'ehetso ea Process-Node
Netefatsa ts'ehetso bakeng sa foundry e khethiloeng, process node, voltage option, metal stack, mocheso, le netefatso e hlokahalang.
Mohato 5: Sheba Ts'ehetso ea Protocol
Netefatsa ts'ehetso bakeng sa PCIe, CXL, streaming, kapa protocol mapping e khethiloeng e sebelisoang ke chiplets. Hape netefatsa hore SoC interfaces tse hlokahalang li teng.
Mohato 6: Sheba Matla, Latency, le Area
Sheba matla a ho sebetsa le a idle, latency ho tloha qaleho ho qaleho, PHY area, le controller area. Litlhoko tsena li lokela ho khethoa ho kenyelletsa matla, mocheso, le meeli ea die-area.
Mohato 7: Sheba Likaroloana tsa Test le Repair
Batla loopback, ho kenya liphoso, CRC counters, lane repair, mesebetsi ea tlhahlobo, le likarolo tse ling tse hlokahalang bakeng sa ho qala le ho hlahloba liphoso.
Mohato 8: Netefatsa Ts'ehetso ea Verification
Etsa sicher lisebelisoa tsa netefatso li kgethe protocol checks, compliance tests, FDI le RDI interfaces, liphetho tse fosahetseng, le ts'ebetso e felletseng.
Mohato 9: Sheba Ts'ehetso le Lifecycle
Sheba documentation, mehlala, litlhoko tsa firmware, ts'ehetso ea theknoloji, merero ea tlhokomelo, le leano la sehlahisoa. Ts'ehetso ea nako e telele e bohlokoa bakeng sa mehopolo e nang le bophelo bo bolelele ba tlhahiso.
Mohato 10: Sheba Interoperability
Chiplets tse peli li ka tšehetsa UCIe version e tšoanang empa li sitwa ho sebetsa hammoho. Kopa liphetho tsa interoperability ho sebelisa controller, PHY, data rate, lane count, paket, protocol, process node, le likaroloana tsa recovery.
UCIe link e lokela ho hlahlobisoe pele ho tape-out, nakong ea ho etsa paket, ka mor'a ho kopanya, le nakong ea ho qala tsamaiso.
| sethala ea teko |
Likhohlano tse kholo |
| Netefatso e Pele-silicon |
Tlhakisa, koetliso, protocol, maemo a matla, CRC, retry, liphoso, le lane repair |
| Simulation channel-paket |
Lahleheloa, reflections, crosstalk, skew, liphetoho tsa impedance, le eye margin |
| PHY compliance |
Nako ea moetsi, jitter, margin ea moameli, BER, lane skew, le nako e tlase ea matla |
| Teko ea protocol |
Order e nepahetseng ea data, CRC detection, retry, flow control, le lane repair |
| Teko ea Interoperability |
Ts'ebetso ea controller e nepahetseng, PHY, paket, rate, lane count, le protocol combination |
E hokahanya moetsi ea reretsoeng le PHY ka mor'a moralo oa paket. Hlahloba litekanyo tsohle tse tšehetsang le bophara ba lane, ebe u netefatsa qaleho, koetliso, data transfer, liphetoho tsa maemo a matla, CRC, retry, lane repair, le ho tlatsa liphetho.
Phetolo liketso ho phahamisa motlakase le mocheso. Rekota litekanyo tse amanang, mekhahlelo e sebetsang, BER, retries, bandwidth, latency, le litlhahiso tse nepahetseng.
| Bothata |
Likhohlano tse kholo |
Mothomelo o ka khoneha |
| Sehokelo ha se qalehe |
Tsoela pele, nako, matla, mokhoa, le li-setting tse ling |
Nako e nepahetseng, matla, nako, firmware, kapa mokhoa |
| Link e trenileng ka lebelo le tlase |
Lebelo le buisanwang, bophara ba laeborari, BER, sebaka sa leihlo, ho lahleheloa, le cross-talk |
Lokisa ho tsamaisa, li-setting tse nepahetseng, kapa sebelisa lebelo le tšehetsoeng le tlase |
| BER e phahameng |
Jitter, skew, reflection, ho lahleheloa ke channel, le mollo oa matla |
Eketsa impedance, ho tsamaisa, sebaka, filtering, kapa PHY tuning |
| Bandwidth e tlase |
Lanes tse sebetsoeng, lebelo la link, ho pheta-pheta, taolo ea potoloho, le litekanyetso tse ka hare |
Fokotsa mago, tlosa liphoso, eketsa buffer, kapa ho pharalla tsela ea ka hare |
| Latency e fetelletseng |
Lisebelisoa, ho cross ea nako, ho pheta-pheta, ho tletse, le maemo a matla |
Fokotsa buffering, lokisa liphoso, kapa lokisa policy ea matla |
| Phoso ea ts'ebeliso e amanang |
Mefuta e tšepahalang, mekhahlelo, li-setting tsa FDI/RDI, firmware, le likarolo tse khethehileng |
Lokisetsa li-setting kapa sebelisa kopanyo ea IP e lekantsoeng |
Liphumano tse hlahlobiloeng li lokela ho se thusa version ea UCIe, liphetoho tsa IP, phakete, lebelo la data, palo ea lane, voltage, temperature, protocol, mokhoa oa sephethephethe, nako, le moeli o atlehileng kapa o flopang.
UCIe e loketse ha liphetho tse ngata li hloka puisano e kholo e amanang le phakete e le 'ngoe. E ntse e se loketse bakeng sa mehlala e bonolo, e tlase, kapa e amanang le litheko.
| Sebelisa UCIe ha |
Nahana ka interface e 'ngoe ha |
| Liphetho tse ngata li fetotse mekhahlelo e mengata ea data |
Moralo o loketse hantle holim'a die e le 'ngoe |
| Bophara bo phahameng ba phakete bo hlokahala |
Link e etsa feela data ea taolo e tlase-tlhase |
| Liphetho tse bohlokoa li karolo ea moralo oa sehlahisoa |
Theko ea phakete e lokela ho lula e tlase haholo |
| Mehlodi e fapaneng e hloka mekhahlelo e fapaneng ea phetoho |
Link e bonolo ea borai kapa ea borai e lekane |
| PCIe, CXL, kapa sephethephethe se streaming lokela ho feta pakeng tsa die |
UCIe IP e loketseng ha e fumanehe |
| Ts'ehetso ea barekisi ba bangata e hlokahala |
Tlhahlobo ea phakete le interoperability e sitwa ho tšehetsoa |
UCIe ke khetho e ntle ha bophara ba eona, borai ba chiplet, le flexibiility ea mofuta ofe kapa ofe e fana ka lebaka la ho eketsa ho empa, ho hlahloba, le ho netefatsa mesebetsi.
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Qala ka bophara bo theohetseng: lane rate × active lanes × mekhahlelo ÷ 8. Bophara ba lesela la 'nete bo tlase hobane mekhahlelo ea protocol, CRC, ho pheta-pheta, taolo ea potoloho, le nako e bonahalang li sebelisa karolo ea bokhoni ba link. Mosebetsi o amanang o lokela ho kenyelletsa ha u kenya link.
Link e nang le 16 lanes ho 48 GT/s e fa 96 GB/s ea bophara bo theohetseng ho each direction. Haeba efficiency ea payload e le 80%, e mong le e mong o ka tlase ho 76.8 GB/s e setseng bakeng sa data ea kopo, ka hona e ke ke ea fihlela 80 GB/s tefo ea payload.
UCIe-S e loketse ho thepa e theko e tlase le lihlahisoa tse telele channels. UCIe-A e tšehetsa mekhahlelo e metle le bongata bo phahameng ba ho amanang, ha UCIe-3D e etselitsoe litemoso tseo li amanang ka nepo. Theko ea phakete, ho tsamaisa, meeli ea mocheso, le bothata ba ho kopanya bo lokela ho hlokomelwa hape.
Che. Chiplets tse peli li ka tšehetsa version e tšoanang ea UCIe empa li ka ntse li fapane ka li-setting tsa PHY, mekhahlelo ea protocol, mehopolo ea phakete, firmware, lane configuration, kapa likarolo tse amanang. Interoperability e lokela ho hlahlojoa ho sebelisa configuration e ratoa bakeng sa production.
Lanes tse ngata li eketsa bophara bo kakgethwa, empa li boetse li sebelisa sebaka se ngata sa die-edge , bumps, ho tsamaisa phakete, lisebelisoa tsa nako, le matla a PHY. Palo ea lane e lokela ho finsa sepheo sa bophara ntle le ho eketsa sebaka le matla a sa hlokahaleng.
Mehloli e tloaelehileng e kenyelletsa sebaka se mpe sa leihlo, ho lahleheloa ke channel e feteletseng, cross-talk, jitter, mathata a lane, kapa configuration e sa nepahetseng. Ho lelekisa lebelo le buisanwang, BER, bophara ba lane, channel ea phakete, le li-setting tsa PHY ho ka thusa ho fumana bothata.
Imeile: Info@ariat-tech.comMohala HK: +852 30501966Aterese: Kamore 2703 Mokatong wa 27 Ho King Comm Center 2-16,
Seterata sa Fa Yuen MongKok Kowloon, Hong Kong.